1. Technical Field
The present invention relates to a design structure for improved logic simulation. More particularly, the present invention relates to a design structure for improving logic simulation by using a negative unknown Boolean state that is maintained by the logic simulator.
2. Description of the Related Art
Logic designs described in Register Transfer Level (RTL) code and netlists are typically simulated using logic simulators. Netlists are traditionally created by “synthesizing” the RTL design into circuits that use the library elements of the target technology library, such as basic AND gates, OR gates, flip-flops, and the like. Both the RTL representation of the design as well as the resulting netlist are usually expressed using the same Hardware Description Language (HDL). Examples of Hardware Description Languages include Verilog and VHDL.
Simulators keep track of the “state” of each memory element (such as a latch or flip-flop) and each net in the design. At any given time, a memory element can be in one of a few states. In a traditional simulator, these states include ‘1’, ‘0’, and ‘X’, where ‘X’ is an unknown Boolean state that indicates that the value of the logic element is unknown to the simulator. The unknown Boolean state may be indicated in different ways in different simulators. For example, an ‘X’ state denotes the unknown Boolean state in Verilog, while a ‘U’ state denotes the unknown Boolean state in VHDL. Despite the differences in notation, most, if not all, simulators accommodate an unknown Boolean state in order to keep track of logic elements that has an unknown Boolean state at a given point in time. The unknown Boolean state is used because it often cannot be known which state (e.g., 0 or 1) any of the numerous logic elements will resolve to when power is applied to the circuit. When a circuit is initially powered on, the value of various logic elements is essentially random (e.g., a given logic element may be in either a high (1) state or a low (0) state, but there is no way of knowing which state (high or low) the logic element initializes to when power is initially applied). Because the design needs to work properly regardless of the initial state of the logic element when power is applied, simulators assign the unknown Boolean state (X) to the logic elements when simulation is commenced.
In most circuits, a reset signal is used to force all necessary values to a known state (e.g., either 0 or 1). However, a challenge in current simulators, is that not all logic elements need to be reset. Some elements can remain in the unknown Boolean state (X) until the element is actually used in the design. One challenge faced by circuit designers is that design compilers and other logic synthesizers can create logic that does not properly reset when simulated due to the unknown Boolean states not properly clearing, even though the circuit design (the Hardware Design Language) and the resulting netlist logic is correct. This is because, once built, the actual hardware circuit will reset properly regardless of whether a logic element powers up high (1) or low (0). However, due to the way that the circuit is design and the way that the simulator handles unknown Boolean states, the simulator does not properly clear the unknown Boolean states. This results in the simulator generating false errors.
A few approaches have been developed to address the aforementioned challenge. A reset signal can be introduced at the last stage of a circuit. However, this approach is problematic because the last stage of a circuit is often on the critical path of the circuit which is often not an optimal place to introduce a reset signal. In a timing-critical circuit, introducing the reset signal at the last stage of the circuit can cause the circuit to miss timing requirements. Another approach that designers use is to “force” the reset of various unresolved simulated logic element signals in order to avoid false errors from the simulator. The forcing is done via the simulator and is not part of the design. The use of these forced reset signals can result in masking actual problems in the circuit design (e.g., where the circuit does not properly power up but the introduction of forced reset signals masks the error in the simulation of the circuit's power up sequence). The designer must be very careful to force only false errors. That approach is error prone because the list of logic elements to force can change each time synthesis is run leaving, the possibility that logic elements on the current list should not be on the next list. Consequently, using this approach the designer needs to ascertain which logic elements need to be both added and removed with each synthesis run.
FIG. 1A is a circuit diagram that depicts how the prior art's handling of unknown Boolean states can cause false errors, especially when simulating the power-on sequence of a circuit. Circuit 100 is a simple circuit where the signal from logic gate 140 is fed back into the circuit. In traditional simulators, the output (Q) from logic gate 140 is initialized to an unknown Boolean state (X). This unknown Boolean state is fed to inverter 110. However, the inverse of an unknown Boolean state is still an unknown Boolean state (X). AND gate 120 receives the output from the inverter (unknown Boolean state (X)) and the reset signal which forces a high value (1) as an input to AND gate 120. However, AND gate 120 outputs another unknown Boolean state when it ANDs the unknown Boolean state with the high (1) state of the reset signal. NOR gate 130 then receives both the output from AND gate 120 and the unknown Boolean state fed from logic gate 140. This causes NOR gate 130 to also output an unknown Boolean state (X) which is fed back to logic gate 140, causing an error.
If circuit 100 were actually built, however, it can be shown that the circuit would properly initialize regardless of whether logic gate 140 randomly initiated to a high (1) state or a low (0) state. When power is applied to circuit, if logic gate 140 is in a high state (1), the high value (1) would be fed to inverter 110 resulting in a low value (0) being fed to AND gate 120 along with the reset signal (1). The AND gate would output a 0 (1 ANDed with 0 being 0). The 0 from AND gate 120 would be fed to NOR gate 130 along with the random high (1) state fed from logic gate 140 resulting in a low value output fed to logic gate 140 (0 NORed with 1 being 0). Likewise, if the circuit powered up to a low (0) state, the 0 would be fed to inverter 110 resulting in a high value (1). The ANDing of the high value (1) with the reset signal (1) at AND gate 120 would result in a high value (1) being output from AND gate 120 and fed to NOR gate 130. NOR gate 130 receives the high value (1) from AND gate 120 and the random low (0) state fed from logic gate 140. Once again, the NOR of the 1 and the 0 would result in a 0 being fed to logic gate 140. In other words, while the simulator indicated an error condition during power up, the actual circuit would properly power up regardless of the random value initially output from logic gate 140.